DMP Electronics eBOX-3350MX-AP Instrukcja Użytkownika Pobierz pdf (Strona 40)

Jan Yin Chan Electronics Co.,LTD. 386SX Single Chip PC

M6117D : System on a chip

DM&P

Jan Yin Chan Electronics Co,. LTD. M6117D 386SX Single Chip PC Page 39

8F-1,No.22,Wuchyuan 2RD.,Hsin Chuang city Taipei Hsien, Taiwan, R.O.C. Tel: 886-(02) 2298-0770 Fax: (02) 2299-1883

4.12.1 How to setting General Purpose Chip Select ?

(1) Set Index 44h : D[0] to decide GPCS0J represent memory or I/O access.

(2) Set Index 41h : D[7~0] and Index 40h : D[7~1] to decide starting address A[25-11] or A[15-1] depend on memory or I/O,

respectively.

(3) Set Index 43h : D[7~0] and Index 42h : D[7~1] to decide the address range by mask A[25-11] or A[15-1] depend on

memory or I/O, respectively. E.g. for memory case, mask A[11] will cause no comparison of A[11], which means the

decode cover 4K byte memory range started from starting address defined in step (2).

(4) Set Index 40h : D[0] = 1 to enable GPCS0J. If GPCS0J represent address decode only, then the procedure is finished.

(5) If GPCS0J need to

“filter” out read or write command, then Index 44h : D[5~2] can be used to select read or write

command to qualify decode. I.e. for memory access case, set Index 44h : D[2] = 1 cause GPCS0J active only happen

when I/O read cycle. This is typical case to protect device from incorrectly write data in.

Please refer to see Appendix.

4.12.1 How to setting General Purpose Chip Select ?

GPCS

OUTPUT

AEN

4.12 Register Summary

Internal

Bus

15 bit address latch and

control bus latch Index

40h, 41h, 48h, 49h, 45h

Mask bit control

Index 42h, 43h, 4Ah,

4Dh

Gate

Address

Multiplex

I/O,A[15-1]

Mem,A[25-11

]

GPCS I/O or Memory

Index 44h, 45h,

Bit 0

GPCS Enable

Index 40h, 48h

Bit 0

8/16 Bit Data bus control

Index 44h, 45h,

Bit 1

1 2 ... 35 36 37 38 39 40 41 42 43 44 45 ... 111 112

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