DMP Electronics eBOX-3350MX-AP Instrukcja Użytkownika Pobierz pdf (Strona 38)

Jan Yin Chan Electronics Co.,LTD. 386SX Single Chip PC

M6117D : System on a chip

DM&P

Jan Yin Chan Electronics Co,. LTD. M6117D 386SX Single Chip PC Page 37

8F-1,No.22,Wuchyuan 2RD.,Hsin Chuang city Taipei Hsien, Taiwan, R.O.C. Tel: 886-(02) 2298-0770 Fax: (02) 2299-1883

The watchdog timer uses 32.768 kHz frequency source to count a 24-bit counter so the time range is from 30.5u sec to 512

sec with resolution 30.5u sec. When timer times out, a system reset, NMI or IRQ may happen to be decided by BIOS

programming. Please refer to see Appendix.

4.10.1 How to set the watchdog timer function ?

Index 37h :

Bit 6 = 0, Disable watchdog timer

Bit 6 = 1, Enable watchdog timer

Bit 7 = 0, Counter read mode. When read from index 3Bh, 3Ah, 39h, the return value is the setting counter value

Bit 7 = 1, Counter read mode. When bit 7 set from 0 to 1, the counter present value will be latched to buffer. When

read from 3Bh, 3Ah, 39h, the return value is the buffer value. The counter will keep on counting.

Index 3Ch:

Bit 7 = 0, Read only, Watchdog timer time out event does not happen.

Bit 7 = 1, Read only, Watchdog timer time out event happens.

Index 3Bh, 3Ah, 39h : Counter

3Bh 3Ah 39h

D7……D0 D7……D0 D7……D0

Counter

Most SBit ………………………………

east SBit

4.10.2 How to set the watchdog timer counter ?

(1) Set Bit 6 = 0 to disable the timer

(2) Write the desired counter value to 3Bh, 3Ah, 39h.

(3) Set Bit 6 = 1 to enable the timer, the counter will begin to count up.

(4) When counter reaches the setting value, the time out will generate signal setting by index 38h bit[7:4]

(5) BIOS can read index 3Ch Bit 7 to decide whether the Watchdog timeout event will happen or not.

Index 38h : Bit[7:4] : time out generate signal select

Index 38h

D[7:4]

timeout generate

signal

0000 Reserved

0001 IRQ3

0010 IRQ4

0011 IRQ5

0100 IRQ6

0101 IRQ7

0110 IRQ9

0111 IRQ10

1000 IRQ11

1001 IRQ12

1010 IRQ14

1011 IRQ15

1100 NMI

1101 System reset

1110 Reserved

1111 Reserved

4.10.3 How to read the watchdog timer counter value when its counting ?

(1) Set Bit 7 = 1 to latch value

(2) Read the value in register index 3Bh,3Ah,39h. Then this is the on going value of counter.

4.10.4 How to clear the watchdog timer counter ?

(1) Set Bit 6 = 0 to disable timer. This will also clear counter at the same time.

4.10.4 Watchdog timer block diagram

1 2 ... 33 34 35 36 37 38 39 40 41 42 43 ... 111 112

Komentarze do niniejszej Instrukcji

Brak uwag

DMP Electronics eBOX-3350MX-AP Instrukcja Użytkownika Strona 38

Komentarze do niniejszej Instrukcji

Powiązane produkty i podręczniki dla Części komputerowe DMP Electronics eBOX-3350MX-AP